Visual Micro Lab is a new design tool for the ST6 micro. It allows you to build applications without the need of an emulator.

Avertec is a new company specialising in the commercialisation of innovative VLSI verification tools developed in University research laboratories. Its main areas of expertise are in hierarchical timing analysis and the automatic abstraction of behavioural model from circuit netlists.

CAD EDA PCB Software

CAD EDA EAGLE Layout Editor

3D Electromagnetic Simulation and Optimization, as well as File Format Translators.

Provides electronic design automation software products focussing on systems design including schematic capture, board and electromechanical design and manufacturing. Online product descriptions and demonstration software and sample data available for download.

Silicon debug, JTAG, boundary scan, IEEE 1149.1, scan-based electronic design verification, and test solutions from Intellitech Corporation.

Uses JTAG, for testing and in-system programming (ISP) printed circuit boards and systems.

This site provides information regarding boundary-scan JTAG testing, JTAG In-System-Programming of Flash memories and CPLDs, JTAG emulation and debugging.

EDA start up offering a physical design solution claiming guaranteed accurate prediction and delivery of the best possible timing results, without iterations.

Qcad 10.1 is a complete schematic and PCB design software together with an autorouter and a post routing optimizer.

Software tools for EDA, VHDL and Verilog model generation, simulation, and timing diagram editor.