For advanced hobbyists: share free microprocessor and DSP IP cores written in Verilog or VHDL.

Project to design and implement scaleable RISC microprocessor for embedded applications. All architecture and source code to be released under GNU General Public License, or a slightly modified version that includes hardware, not only software.

Initial announcement of the GPLed LEON SPARC architecture.

Functional SPARC compatible processor core integer unit. Runs on Altera, Mietec, Temic MG2, Xilinx. Developed for space missions. Implemented as a highly configurable, synthesisable GPL VHDL model.

A core is the central component of a microprocessor or controller chip. Chips using picoJava core are ideally suited for consumer electronic products running Java applications. By Sun Microsytems, Sun Community Source License.

Sun Microsystems announces: for research uses, it extends its new Community Source Licensing model to picoJava and SPARC architectures; the first time a company made major microprocessor intellectual property available via open licensing.

32-bit, 2-way superscalar RISC processor, designed in a HDL. Source downloads. This one is actually working.

Mainly dedicated to purely SIMD superpipelined 64-bit RISC CPU, and the sources distributed under the terms of the GNU licence.

32-bit microprocessor architecture developed to serve as the main hardware building block of the real-time TRON Hypernetwork (Highly Functional Distributed System: HFDS), which is the ultimate goal of the TRON Project.