Breakthrough in logic verification. Funded by very experienced people from EDA

The Spyglass suite of tools uses predictive analysis technique that performs structural analysis on Verilog and VHDL RTL to detect design problems in SoCs and ASICs.

EDA tools such as a VHDL/Verilog RTL source level debugger, which instruments the target circuit with custom debugging logic.

Enabling Excellence in VLSI Design, VLSI, ASIC, FPGA:- CG-CoreEl Programmable Solutions provides design services on FPGAs and ASICs in the areas of Telecom, Datacom, Networking and Digital Signal processing. The emphasis is on fast time to market. We at CG-CoreEl are leveraging the vast experience and a wealth of Telecom and Networking IP to deliver solutions on FPGAs and ASICs to suit your design needs and your design schedules.

John Cooley's independent newsletter on Synthesis and related silicon design automation software. Originally the e-mail Synopsys Users Group (ESNUG). A compiled set of emails contributed by synthesis tool users and edited by John along with his columns and industry analysis. Many discussions of inter vendor issues and workarounds. Very piquant observations with good understanding of technology.

Develops software which aids your ASIC flow from design through verification.

An Open Source interactive simulator frontend for Verilog and VHDL circuit simulation.

A merging of design software companies, which creates a complete PC based design environment. This includes everything from ASIC design to PCB design.

Provides the VerilogTool software and IP for creating and managing digital designs.

Tools for FPGA design and testing, evaluation boards for FPGA prototyping, hardware and system design consulting.

Tharas Systems, Inc. provides hardware accelerated RTL simulation for SoC, up to 1000x the performance of software based simulators.

Developers of innovative design verification and coverage software.